v_mqsad_u32_u8 GPU Native ISA AMD Vector

Vector Arithmetic

v_mqsad_u32_u8

Perform the V_MSAD_U8 operation four times using different slices of the first array, all entries of the second array and each entry of the third…

Encoding

Binary Layout (AMD CDNA 5)
NEG
63:61
OMOD
60:59
SRC2
58:50
SRC1
49:41
SRC0
40:32
110101
31:26
1000111101
25:16
CLAMP
15
OPSEL
14:11
ABS
10:8
VDST
7:0
 

The ENC_VOP3 layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 573 in OP rebuilds 0x00000000D63D0000, an identifier AMD lists for this encoding. Not the same in every generation: AMD CDNA 4 (opcode 487, field layout), AMD CDNA 3 (opcode 487, field layout), AMD CDNA 2 (opcode 487, field layout), AMD CDNA 1 (opcode 487, field layout), AMD RDNA 3.5 (field layout), AMD RDNA 3 (field layout), AMD RDNA 2 (opcode 373, field layout), AMD RDNA 1 (opcode 373, field layout). The same in AMD RDNA 4.

Format VOP3
Width 64 bits
Opcode 573
Identifier 0x00000000D63D0000

Operands

  • VDST
    Written. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: 128 bits of arbitrary data. (OPR_VGPR, FMT_NUM_B128)
  • SRC0
    Read. All operands. Covers all operands that are allowed as scalar or vector sources. Data format: 64 bits of arbitrary data. (OPR_SRC, FMT_NUM_B64)
  • SRC1
    Read. All operands. Covers all operands that are allowed as scalar or vector sources. Data format: 32 bits of arbitrary data. (OPR_SRC, FMT_NUM_B32)
  • SRC2
    Read. Operand must be a vector GPR. Uses a 9-bit operand field. Data format: 128 bits of arbitrary data. (OPR_SRC_VGPR, FMT_NUM_B128)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VOP3 encoding (AMD CDNA 5).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Description

Perform the V_MSAD_U8 operation four times using different slices of the first array, all entries of the second array and each entry of the third array. Pack each 32-bit value into a 4-entry array and store the array into a vector register. The first input is an 8-entry array of unsigned 8-bit integers, the second input is a 4-entry array of unsigned 8-bit integers and the third input is a 4-entry array of unsigned 32-bit integers.

Semantics

tmp[127 : 96] = 32'B(v_msad_u8(S0[55 : 24], S1[31 : 0], S2[127 : 96].u32)); tmp[95 : 64] = 32'B(v_msad_u8(S0[47 : 16], S1[31 : 0], S2[95 : 64].u32)); tmp[63 : 32] = 32'B(v_msad_u8(S0[39 : 8], S1[31 : 0], S2[63 : 32].u32)); tmp[31 : 0] = 32'B(v_msad_u8(S0[31 : 0], S1[31 : 0], S2[31 : 0].u32)); D0.b128 = tmp.b128

Example

v_mqsad_u32_u8 v[5:8], -1, -1, v[252:255]

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources