v_mul_u64 GPU Native ISA AMD Vector

Vector Arithmetic

v_mul_u64

AMDGPU VOP2 vector instruction operating on u64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)

Encoding

Binary Layout (AMD CDNA 5)
0
31
101010
30:25
VDST
24:17
VSRC1
16:9
SRC0
8:0
 

The ENC_VOP2 layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 42 in OP rebuilds 0x54000000, an identifier AMD lists for this encoding. No other generation in the specification defines this instruction.

Format VOP2
Width 32 bits
Opcode 42
Identifier 0x54000000

Operands

  • VDST
    Written. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: Unsigned 64-bit integral data. (OPR_VGPR, FMT_NUM_U64)
  • SRC0
    Read. All operands. Covers all operands that are allowed as scalar or vector sources. Data format: Unsigned 64-bit integral data. (OPR_SRC, FMT_NUM_U64)
  • VSRC1
    Read. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: Unsigned 64-bit integral data. (OPR_VGPR, FMT_NUM_U64)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VOP2 encoding (AMD CDNA 5).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Sources