v_msad_u8 GPU Native ISA AMD Vector

Vector Arithmetic

v_msad_u8

Calculate the sum of absolute differences of elements in two packed 4-component unsigned 8-bit integer inputs, except that elements where the second…

Encoding

Binary Layout (AMD CDNA 5)
NEG
63:61
OMOD
60:59
SRC2
58:50
SRC1
49:41
SRC0
40:32
110101
31:26
1000111001
25:16
CLAMP
15
OPSEL
14:11
ABS
10:8
VDST
7:0
 

The ENC_VOP3 layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 569 in OP rebuilds 0x00000000D6390000, an identifier AMD lists for this encoding. Not the same in every generation: AMD CDNA 4 (opcode 484, field layout), AMD CDNA 3 (opcode 484, field layout), AMD CDNA 2 (opcode 484, field layout), AMD CDNA 1 (opcode 484, field layout), AMD RDNA 3.5 (field layout), AMD RDNA 3 (field layout), AMD RDNA 2 (opcode 369, field layout), AMD RDNA 1 (opcode 369, field layout). The same in AMD RDNA 4.

Format VOP3
Width 64 bits
Opcode 569
Identifier 0x00000000D6390000

Operands

  • VDST
    Written. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: Unsigned 32-bit integral data. (OPR_VGPR, FMT_NUM_U32)
  • SRC0
    Read. All operands. Covers all operands that are allowed as scalar or vector sources. Data format: 32 bits of arbitrary data. (OPR_SRC, FMT_NUM_B32)
  • SRC1
    Read. All operands. Covers all operands that are allowed as scalar or vector sources. Data format: 32 bits of arbitrary data. (OPR_SRC, FMT_NUM_B32)
  • SRC2
    Read. All operands. Covers all operands that are allowed as scalar or vector sources. Data format: 32 bits of arbitrary data. (OPR_SRC, FMT_NUM_B32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VOP3 encoding (AMD CDNA 5).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Overflow into the upper bits is allowed.

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Description

Calculate the sum of absolute differences of elements in two packed 4-component unsigned 8-bit integer inputs, except that elements where the second input (known as the reference input) is zero are not included in the sum. Add an unsigned 32-bit integer value from the third input and store the result into a vector register.

Semantics

ABSDIFF = lambda(x, y) ( x > y ? x - y : y - x); // UNSIGNED comparison tmp = S2.u32; tmp += S1.u32[7 : 0] == 8'0U ? 0U : 32'U(ABSDIFF(S0.u32[7 : 0], S1.u32[7 : 0])); tmp += S1.u32[15 : 8] == 8'0U ? 0U : 32'U(ABSDIFF(S0.u32[15 : 8], S1.u32[15 : 8])); tmp += S1.u32[23 : 16] == 8'0U ? 0U : 32'U(ABSDIFF(S0.u32[23 : 16], S1.u32[23 : 16])); tmp += S1.u32[31 : 24] == 8'0U ? 0U : 32'U(ABSDIFF(S0.u32[31 : 24], S1.u32[31 : 24])); D0.u32 = tmp

Example

v_msad_u8 v5, v1, v2, s3

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources