v_mul_f64 GPU Native ISA AMD Vector

Vector Arithmetic

v_mul_f64

Multiply two floating point inputs and store the result into a vector register.

Encoding

Binary Layout (AMD CDNA 5)
0
31
000110
30:25
VDST
24:17
VSRC1
16:9
SRC0
8:0
 

The ENC_VOP2 layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 6 in OP rebuilds 0x0C000000, an identifier AMD lists for this encoding. Not the same in every generation: AMD CDNA 4 (encoding ENC_VOP3, opcode 641, field layout), AMD CDNA 3 (encoding ENC_VOP3, opcode 641, field layout), AMD CDNA 2 (encoding ENC_VOP3, opcode 641, field layout), AMD CDNA 1 (encoding ENC_VOP3, opcode 641, field layout), AMD RDNA 3.5 (layout not verifiable), AMD RDNA 3 (layout not verifiable), AMD RDNA 2 (layout not verifiable), AMD RDNA 1 (layout not verifiable). The same in AMD RDNA 4.

Format VOP2
Width 32 bits
Opcode 6
Identifier 0x0C000000

Operands

  • VDST
    Written. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: 64-bit double-precision floating point value. (OPR_VGPR, FMT_NUM_F64)
  • SRC0
    Read. All operands. Covers all operands that are allowed as scalar or vector sources. Data format: 64-bit double-precision floating point value. (OPR_SRC, FMT_NUM_F64)
  • VSRC1
    Read. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: 64-bit double-precision floating point value. (OPR_VGPR, FMT_NUM_F64)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VOP2 encoding (AMD CDNA 5).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Example

v_mul_f64 v[5:6], -1, -1

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources