v_permlane32_swap_b32 GPU Native ISA AMD Vector

Vector Arithmetic

v_permlane32_swap_b32

Swap data between two vector registers. Rows 2 and 3 of the first operand are swapped with rows 0 and 1 of the second operand (one row is 16 lanes).

Encoding

Binary Layout (AMD CDNA 4)
0111111
31:25
VDST
24:17
01011010
16:9
SRC0
8:0
 

The ENC_VOP1 layout from AMD's machine-readable ISA specification (AMD CDNA 4). Opcode 90 in OP rebuilds 0x7E00B400, an identifier AMD lists for this encoding. No other generation in the specification defines this instruction.

Format VOP1
Width 32 bits
Opcode 90
Identifier 0x7E00B400

Operands

  • VDST
    Written. N/A Data format: N/A (OPR_VGPR, FMT_NUM_B32)
  • SRC0
    Written. N/A Data format: N/A (OPR_SRC_VGPR, FMT_NUM_B32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VOP1 encoding (AMD CDNA 4).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Sources