v_pk_fmac_f16 GPU Native ISA AMD Vector
V PK FMAC F16 Vector Arithmetic
v_pk_fmac_f16
Multiply two packed half-precision float inputs component-wise and accumulate the result into the destination register using fused multiply add.
Encoding
Verified bit-level encoding data is not yet available for this instruction.
The instruction-format classification below (VOP2)
is well-documented and stable; exact per-target opcode/field bit positions have not
yet been imported from a verified source.
Operands
Operand details have not yet been curated for this instruction.
GFX Target Compatibility
| Target | Support |
|---|---|
| gfx1100 | ✅ Supported |
Related
More in Vector Arithmetic
Reference
AMDGPU / GFX ISA
Semantics
D0[15 : 0].f16 = fma(S0[15 : 0].f16, S1[15 : 0].f16, D0[15 : 0].f16);
D0[31 : 16].f16 = fma(S0[31 : 16].f16, S1[31 : 16].f16, D0[31 : 16].f16)
Example
v_pk_fmac_f16 v5, -1, v2A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.
Sources
- User Guide for AMDGPU Backend ↗ - LLVM Project
-
"AMD Instinct MI300" Instruction Set Architecture: Reference Guide ↗
- Advanced Micro Devices, Inc.
Reference Guide, page 185. - LLVM MC assembler tests for AMDGPU (gfx11) ↗ - LLVM Project