v_screen_partition_4se_b32 GPU Native ISA AMD Vector

Vector Arithmetic

v_screen_partition_4se_b32

4SE version of LUT instruction for screen partitioning/filtering.

Encoding

Binary Layout (AMD CDNA 4)
0111111
31:25
VDST
24:17
00110111
16:9
SRC0
8:0
 

The ENC_VOP1 layout from AMD's machine-readable ISA specification (AMD CDNA 4). Opcode 55 in OP rebuilds 0x7E006E00, an identifier AMD lists for this encoding. The same in the other 3 generations that define it.

Format VOP1
Width 32 bits
Opcode 55
Identifier 0x7E006E00

Operands

  • VDST
    Written. N/A Data format: N/A (OPR_VGPR, FMT_NUM_B32)
  • SRC0
    Read. N/A Data format: N/A (OPR_SRC, FMT_NUM_B32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VOP1 encoding (AMD CDNA 4).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Description

4SE version of LUT instruction for screen partitioning/filtering. This opcode is intended to help accelerate screen partitioning in the 4SE case only. 2SE and 1SE cases use normal ALU instructions.

Example

v_screen_partition_4se_b32 v5, 0

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx9_asm_vop1.s). Not from an AMD document, and not authored here.

Sources