v_sub_nc_u32 GPU Native ISA AMD Vector

Vector Arithmetic

v_sub_nc_u32

Subtract the second unsigned 32-bit integer input from the first input and store the result into a vector register. No carry-in or carry-out support.

Encoding

Binary Layout (AMD CDNA 5)
0
31
100110
30:25
VDST
24:17
VSRC1
16:9
SRC0
8:0
 

The ENC_VOP2 layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 38 in OP rebuilds 0x4C000000, an identifier AMD lists for this encoding. The same in the other 5 generations that define it.

Format VOP2
Width 32 bits
Opcode 38
Identifier 0x4C000000

Operands

  • VDST
    Written. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: Unsigned 32-bit integral data. (OPR_VGPR, FMT_NUM_U32)
  • SRC0
    Read. All operands. Covers all operands that are allowed as scalar or vector sources. Data format: Unsigned 32-bit integral data. (OPR_SRC, FMT_NUM_U32)
  • VSRC1
    Read. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: Unsigned 32-bit integral data. (OPR_VGPR, FMT_NUM_U32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VOP2 encoding (AMD CDNA 5).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Sources