v_subrev_f32 GPU Native ISA AMD Vector

Vector Arithmetic

v_subrev_f32

Subtract the first floating point input from the second input and store the result into a vector register.

Encoding

Binary Layout (AMD CDNA 5)
0
31
000101
30:25
VDST
24:17
VSRC1
16:9
SRC0
8:0
 

The ENC_VOP2 layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 5 in OP rebuilds 0x0A000000, an identifier AMD lists for this encoding. Not the same in every generation: AMD CDNA 4 (opcode 3), AMD CDNA 3 (opcode 3), AMD CDNA 2 (opcode 3), AMD CDNA 1 (opcode 3). The same in AMD RDNA 4, AMD RDNA 3.5, AMD RDNA 3, AMD RDNA 2, AMD RDNA 1.

Format VOP2
Width 32 bits
Opcode 5
Identifier 0x0A000000

Operands

  • VDST
    Written. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: 32-bit single-precision floating point value. (OPR_VGPR, FMT_NUM_F32)
  • SRC0
    Read. All operands. Covers all operands that are allowed as scalar or vector sources. Data format: 32-bit single-precision floating point value. (OPR_SRC, FMT_NUM_F32)
  • VSRC1
    Read. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: 32-bit single-precision floating point value. (OPR_VGPR, FMT_NUM_F32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VOP2 encoding (AMD CDNA 5).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

0.5ULP precision, denormals are supported.

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Semantics

D0.f32 = S1.f32 - S0.f32

Example

v_subrev_f32 v5, -1, v2

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources