v_swap_b32 GPU Native ISA AMD Vector

Vector Arithmetic

v_swap_b32

Swap the values in two vector registers.

Encoding

Binary Layout (AMD CDNA 5)
0111111
31:25
VDST
24:17
unassigned
16
1100101
15:9
SRC0
8:0
 

The ENC_VOP1 layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 101 in OP rebuilds 0x7E00CA00, an identifier AMD lists for this encoding. Bits marked unassigned have no field in the specification. Not the same in every generation: AMD CDNA 4 (opcode 81, field layout), AMD CDNA 3 (opcode 81, field layout), AMD CDNA 2 (opcode 81, field layout), AMD CDNA 1 (opcode 81, field layout), AMD RDNA 3.5 (field layout), AMD RDNA 3 (field layout), AMD RDNA 2 (field layout), AMD RDNA 1 (field layout). The same in AMD RDNA 4.

Format VOP1
Width 32 bits
Opcode 101
Identifier 0x7E00CA00

Operands

  • VDST
    Written. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: 32 bits of arbitrary data. (OPR_VGPR, FMT_NUM_B32)
  • SRC0
    Written. Operand must be a vector GPR. Uses a 9-bit operand field. Data format: 32 bits of arbitrary data. (OPR_SRC_VGPR, FMT_NUM_B32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VOP1 encoding (AMD CDNA 5).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Input and output modifiers not supported; this is an untyped operation.

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Semantics

tmp = D0.b32; D0.b32 = S0.b32; S0.b32 = tmp

Example

v_swap_b32 v5, v1

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources