v_sin_f32 GPU Native ISA AMD Vector

Vector Arithmetic

v_sin_f32 VDST, S0

Per-lane fast approximate sine.

Encoding

Binary Layout (AMD CDNA 5)
0111111
31:25
VDST
24:17
unassigned
16
0110101
15:9
SRC0
8:0
 

The ENC_VOP1 layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 53 in OP rebuilds 0x7E006A00, an identifier AMD lists for this encoding. Bits marked unassigned have no field in the specification. Not the same in every generation: AMD CDNA 4 (opcode 41, field layout), AMD CDNA 3 (opcode 41, field layout), AMD CDNA 2 (opcode 41, field layout), AMD CDNA 1 (opcode 41, field layout), AMD RDNA 3.5 (field layout), AMD RDNA 3 (field layout), AMD RDNA 2 (field layout), AMD RDNA 1 (field layout). The same in AMD RDNA 4.

Format VOP1
Width 32 bits
Opcode 53
Identifier 0x7E006A00
Execution Unit Vector ALU
Register Classes VGPR

Operands

  • VDST
    Destination VGPR
  • S0
    Source operand (radians, pre-scaled per hardware convention)

GFX Target Compatibility

TargetSupport
gfx942✅ Supported
gfx1100✅ Supported

Related PTX Concepts

Special-Function Approximation ↗
equivalent with restrictions
rsqrt (PTX)
sin (PTX)
lg2 (PTX)
sqrt (PTX)
rcp (PTX)

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Description

Calculate the trigonometric sine of a single-precision float value using IEEE rules and store the result into a vector register. The operand is calculated by scaling the vector input by 2 PI.

Semantics

VDST[lane] ≈ sin(S0[lane].f32) for each active lane, valid over a hardware-defined input range.

Example

v_sin_f32  v1, v0   // v1 = approx(sin(v0))

Original illustrative example, written for this site (not reproduced from a specific AMD document).

Sources