v_sub_co_u32 GPU Native ISA AMD Vector

Vector Arithmetic

v_sub_co_u32

Subtract the second unsigned 32-bit integer input from the first input, store the result into a vector register and store the carry-out mask into a…

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (VOP2) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format VOP2

Operands

  • 1: VGPR
    Vector general-purpose register, one value per lane. Written v5 in the assembler example.
  • 2: SGPR
    Scalar general-purpose register, uniform across the wavefront. Written s6 in the assembler example.
  • 3: VGPR
    Vector general-purpose register, one value per lane. Written v1 in the assembler example.
  • 4: VGPR
    Vector general-purpose register, one value per lane. Written v2 in the assembler example.

Register classes read from the LLVM assembler example on this page. No source this site uses names these operands, so no names are given.

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

In VOP3 the VCC destination may be an arbitrary SGPR-pair. Supports saturation (unsigned 32-bit integer domain).

Related PTX Concepts

Subtract with Borrow-Out ↗
equivalent with restrictions
sub.cc (PTX)

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Description

Subtract the second unsigned 32-bit integer input from the first input, store the result into a vector register and store the carry-out mask into a scalar register.

Semantics

tmp = S0.u32 - S1.u32; VCC.u64[laneId] = S1.u32 > S0.u32 ? 1'1U : 1'0U; // VCC is an UNSIGNED overflow/carry-out for V_SUBB_CO_U32. D0.u32 = tmp.u32

Example

v_sub_co_u32 v5, s6, v1, v2

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources