v_sub_f32 GPU Native ISA AMD Vector

V SUB F32 Vector Arithmetic

v_sub_f32 VDST, S0, S1

Per-lane single-precision floating-point subtract.

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (VOP2) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format VOP2
Width 32 bits
Execution Unit Vector ALU
Register Classes VGPR

Operands

  • VDST
    Destination VGPR
  • S0
    Minuend
  • S1
    Subtrahend

GFX Target Compatibility

TargetSupport
gfx942✅ Supported
gfx1100✅ Supported

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Description

Subtract the second floating point input from the first input and store the result into a vector register.

Semantics

VDST[lane] = S0[lane].f32 - S1[lane].f32 for each active lane.

Example

v_sub_f32  v2, v0, v1   // per-lane v2 = v0 - v1

Original illustrative example, written for this site (not reproduced from a specific AMD document).

Sources