v_subbrev_co_u32 GPU Native ISA AMD Vector

Vector Arithmetic

v_subbrev_co_u32

Subtract the first unsigned 32-bit integer input from the second input, subtract a bit from the carry-in mask, store the result into a vector…

Encoding

Binary Layout (AMD CDNA 4)
0
31
011110
30:25
VDST
24:17
VSRC1
16:9
SRC0
8:0
 

The ENC_VOP2 layout from AMD's machine-readable ISA specification (AMD CDNA 4). Opcode 30 in OP rebuilds 0x3C000000, an identifier AMD lists for this encoding. The same in the other 3 generations that define it.

Format VOP2
Width 32 bits
Opcode 30
Identifier 0x3C000000

Operands

  • VDST
    Written. N/A Data format: N/A (OPR_VGPR, FMT_NUM_U32)
  • vcc (1)
    Written. Written in the assembly; this encoding has no field for it. N/A Data format: N/A (OPR_VCC, FMT_NUM_M64)
  • SRC0
    Read. N/A Data format: N/A (OPR_SRC_NOLDS, FMT_NUM_U32)
  • VSRC1
    Read. N/A Data format: N/A (OPR_VGPR, FMT_NUM_U32)
  • vcc (2)
    Read. Written in the assembly; this encoding has no field for it. N/A Data format: N/A (OPR_VCC, FMT_NUM_M64)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VOP2 encoding (AMD CDNA 4).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

In VOP3 the VCC destination may be an arbitrary SGPR-pair, and the VCC source comes from the SGPR-pair at S2.u. Supports saturation (unsigned 32-bit integer domain).

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Description

Subtract the first unsigned 32-bit integer input from the second input, subtract a bit from the carry-in mask, store the result into a vector register and store the carry-out mask into a scalar register.

Semantics

tmp = S1.u32 - S0.u32 - VCC.u64[laneId].u32; VCC.u64[laneId] = 64'U(S0.u32) + VCC.u64[laneId].u64 > 64'U(S1.u32) ? 1'1U : 1'0U; // VCC is an UNSIGNED overflow/carry-out for V_SUBB_CO_U32. D0.u32 = tmp.u32

Example

v_subbrev_co_u32 v5, vcc, 0, v2, vcc

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx9_asm_vop2.s). Not from an AMD document, and not authored here.

Sources