v_swap_b16 GPU Native ISA AMD Vector

Vector Arithmetic

v_swap_b16

Swap the values in two vector registers.

Encoding

Binary Layout (AMD CDNA 5)
0111111
31:25
VDST
24:17
unassigned
16
1100110
15:9
SRC0
8:0
 

The ENC_VOP1 layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 102 in OP rebuilds 0x7E00CC00, an identifier AMD lists for this encoding. Bits marked unassigned have no field in the specification. Not the same in every generation: AMD RDNA 3.5 (field layout), AMD RDNA 3 (field layout). The same in AMD RDNA 4.

Format VOP1
Width 32 bits
Opcode 102
Identifier 0x7E00CC00

Operands

  • VDST
    Written. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: 16 bits of arbitrary data. (OPR_VGPR, FMT_NUM_B16)
  • SRC0
    Written. Operand must be a vector GPR. Uses a 9-bit operand field. Data format: 16 bits of arbitrary data. (OPR_SRC_VGPR, FMT_NUM_B16)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VOP1 encoding (AMD CDNA 5).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Example

v_swap_b16 v5.l, v1.h

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources