v_sub_u32 GPU Native ISA AMD Vector

Vector Arithmetic

v_sub_u32

Subtract the second unsigned 32-bit integer input from the first input and store the result into a vector register. No carry-in or carry-out support.

Encoding

Binary Layout (AMD CDNA 4)
0
31
110101
30:25
VDST
24:17
VSRC1
16:9
SRC0
8:0
 

The ENC_VOP2 layout from AMD's machine-readable ISA specification (AMD CDNA 4). Opcode 53 in OP rebuilds 0x6A000000, an identifier AMD lists for this encoding. The same in the other 3 generations that define it.

Format VOP2
Width 32 bits
Opcode 53
Identifier 0x6A000000

Operands

  • VDST
    Written. N/A Data format: N/A (OPR_VGPR, FMT_NUM_U32)
  • SRC0
    Read. N/A Data format: N/A (OPR_SRC, FMT_NUM_U32)
  • VSRC1
    Read. N/A Data format: N/A (OPR_VGPR, FMT_NUM_U32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VOP2 encoding (AMD CDNA 4).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Supports saturation (unsigned 32-bit integer domain).

Related PTX Concepts

Integer Subtraction ↗
equivalent with restrictions
sub (PTX)

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Semantics

D0.u32 = S0.u32 - S1.u32

Example

v_sub_u32 v5, 0, v2

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx9_asm_vop2.s). Not from an AMD document, and not authored here.

Sources