v_sat_pk_u8_i16 GPU Native ISA AMD Vector
V SAT PK U8 I16 Vector Arithmetic
v_sat_pk_u8_i16
Given 2 signed 16-bit integer inputs, saturate each input over an unsigned 8-bit integer range, pack the resulting values into a packed 16-bit value…
Encoding
Verified bit-level encoding data is not yet available for this instruction.
The instruction-format classification below (VOP1)
is well-documented and stable; exact per-target opcode/field bit positions have not
yet been imported from a verified source.
Operands
Operand details have not yet been curated for this instruction.
GFX Target Compatibility
| Target | Support |
|---|---|
| gfx1100 | ✅ Supported |
Used for 4x16bit data packed as 4x8bit data.
Related
More in Vector Arithmetic
Reference
AMDGPU / GFX ISA
Description
Given 2 signed 16-bit integer inputs, saturate each input over an unsigned 8-bit integer range, pack the resulting values into a packed 16-bit value and store the result into a vector register.
Semantics
SAT8 = lambda(n) (
if n <= 16'0 then
return 8'0U
elsif n >= 16'255 then
return 8'255U
else
return n[7 : 0].u8
endif);
tmp = 16'0;
tmp[7 : 0].u8 = SAT8(S0[15 : 0].i16);
tmp[15 : 8].u8 = SAT8(S0[31 : 16].i16);
D0.b16 = tmp.b16
Example
v_sat_pk_u8_i16 v5.l, v1A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.
Sources
- User Guide for AMDGPU Backend ↗ - LLVM Project
-
"AMD Instinct MI300" Instruction Set Architecture: Reference Guide ↗
- Advanced Micro Devices, Inc.
Reference Guide, page 211. - LLVM MC assembler tests for AMDGPU (gfx11) ↗ - LLVM Project