v_sat_pk_u8_i16 GPU Native ISA AMD Vector

Vector Arithmetic

v_sat_pk_u8_i16

Given 2 signed 16-bit integer inputs, saturate each input over an unsigned 8-bit integer range, pack the resulting values into a packed 16-bit value…

Encoding

Binary Layout (AMD CDNA 5)
0111111
31:25
VDST
24:17
unassigned
16
1100010
15:9
SRC0
8:0
 

The ENC_VOP1 layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 98 in OP rebuilds 0x7E00C400, an identifier AMD lists for this encoding. Bits marked unassigned have no field in the specification. Not the same in every generation: AMD CDNA 4 (opcode 79, field layout), AMD CDNA 3 (opcode 79, field layout), AMD CDNA 2 (opcode 79, field layout), AMD CDNA 1 (opcode 79, field layout), AMD RDNA 3.5 (field layout), AMD RDNA 3 (field layout), AMD RDNA 2 (field layout), AMD RDNA 1 (field layout). The same in AMD RDNA 4.

Format VOP1
Width 32 bits
Opcode 98
Identifier 0x7E00C400

Operands

  • VDST
    Written. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: Unsigned 8-bit integral data. Packed 2-component value. (OPR_VGPR, FMT_NUM_PK2_U8)
  • SRC0
    Read. All operands. Covers all operands that are allowed as scalar or vector sources. Data format: Signed 16-bit integral data. Packed 2-component value. (OPR_SRC, FMT_NUM_PK2_I16)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VOP1 encoding (AMD CDNA 5).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Used for 4x16bit data packed as 4x8bit data.

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Description

Given 2 signed 16-bit integer inputs, saturate each input over an unsigned 8-bit integer range, pack the resulting values into a packed 16-bit value and store the result into a vector register.

Semantics

SAT8 = lambda(n) ( if n <= 16'0 then return 8'0U elsif n >= 16'255 then return 8'255U else return n[7 : 0].u8 endif); tmp = 16'0; tmp[7 : 0].u8 = SAT8(S0[15 : 0].i16); tmp[15 : 8].u8 = SAT8(S0[31 : 16].i16); D0.b16 = tmp.b16

Example

v_sat_pk_u8_i16 v5.l, v1

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources