v_sub_f16 GPU Native ISA AMD Vector
V SUB F16 Vector Arithmetic
v_sub_f16
Subtract the second floating point input from the first input and store the result into a vector register.
Encoding
Verified bit-level encoding data is not yet available for this instruction.
The instruction-format classification below (VOP2)
is well-documented and stable; exact per-target opcode/field bit positions have not
yet been imported from a verified source.
Operands
Operand details have not yet been curated for this instruction.
GFX Target Compatibility
| Target | Support |
|---|---|
| gfx1100 | ✅ Supported |
0.5ULP precision. Supports denormals, round mode, exception flags and saturation.
Related
More in Vector Arithmetic
Reference
AMDGPU / GFX ISA
Semantics
D0.f16 = S0.f16 - S1.f16
Example
v_sub_f16 v5, -1, v2A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.
Sources
- User Guide for AMDGPU Backend ↗ - LLVM Project
-
"AMD Instinct MI300" Instruction Set Architecture: Reference Guide ↗
- Advanced Micro Devices, Inc.
Reference Guide, page 177. - LLVM MC assembler tests for AMDGPU (gfx11) ↗ - LLVM Project