Byte Permute Bit Manipulation
Select and reassemble four arbitrary bytes from two source registers into a destination register.
Vendor-Neutral Definition
d[i] = {a,b}[selector[i]] for each of the 4 destination byte lanes, where selector picks a source byte index (0-7) per lane.
⚠️ Cross-vendor mappings describe semantic relationships and are not guaranteed one-to-one compiler
translations.
equivalent with restrictions
Both select and reassemble bytes from two source registers into a destination register using a per-lane selector.
| Property | NVIDIA PTX | AMDGPU |
|---|---|---|
| Instruction | prmt | v_perm_b32 |
| ISA Layer | Virtual | Native |
| Data Types | - | b32 |
| Version / Target Introduced | PTX ISA 2.0 | gfx1100 |
Important Differences
- PTX's prmt has additional named modes (.f4e, .b4e, .rc8, .ecl, .ecr, .rc16) beyond the generic 4-bit-selector form; only the generic form is a direct match to AMDGPU's v_perm_b32.
Source Evidence
- Parallel Thread Execution ISA ↗ - NVIDIA Corporation
- User Guide for AMDGPU Backend ↗ - LLVM Project
Verification method: documentation