v_cvt_off_f32_i4 GPU Native ISA AMD Vector

V CVT OFF F32 I4 Vector Arithmetic

v_cvt_off_f32_i4

Convert from a signed 4-bit integer input to a single-precision float value using an offset table and store the result into a vector register.

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (VOP1) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format VOP1
Execution Unit

Operands

Operand details have not yet been curated for this instruction.

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Description

Convert from a signed 4-bit integer input to a single-precision float value using an offset table and store the result into a vector register. Used for interpolation in shader. Lookup table on S0[3:0]: S0 binary Result 1000 -0.5000f 1001 -0.4375f 1010 -0.3750f 1011 -0.3125f 1100 -0.2500f 1101 -0.1875f 1110 -0.1250f 1111 -0.0625f 0000 +0.0000f 0001 +0.0625f 0010 +0.1250f 0011 +0.1875f 0100 +0.2500f 0101 +0.3125f 0110 +0.3750f 0111 +0.4375f

Semantics

declare CVT_OFF_TABLE : 32'F[16]; D0.f32 = CVT_OFF_TABLE[S0.u32[3 : 0]]

Example

v_cvt_off_f32_i4 v5, v1

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.

Sources