v_cvt_off_f32_i4 GPU Native ISA AMD Vector

Vector Arithmetic

v_cvt_off_f32_i4

Convert from a signed 4-bit integer input to a single-precision float value using an offset table and store the result into a vector register.

Encoding

Binary Layout (AMD CDNA 5)
0111111
31:25
VDST
24:17
unassigned
16
0001110
15:9
SRC0
8:0
 

The ENC_VOP1 layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 14 in OP rebuilds 0x7E001C00, an identifier AMD lists for this encoding. Bits marked unassigned have no field in the specification. Not the same in every generation: AMD CDNA 4 (field layout), AMD CDNA 3 (field layout), AMD CDNA 2 (field layout), AMD CDNA 1 (field layout), AMD RDNA 3.5 (field layout), AMD RDNA 3 (field layout), AMD RDNA 2 (field layout), AMD RDNA 1 (field layout). The same in AMD RDNA 4.

Format VOP1
Width 32 bits
Opcode 14
Identifier 0x7E001C00

Operands

  • VDST
    Written. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: 32-bit single-precision floating point value. (OPR_VGPR, FMT_NUM_F32)
  • SRC0
    Read. All operands. Covers all operands that are allowed as scalar or vector sources. Data format: Signed 32-bit integral data. (OPR_SRC, FMT_NUM_I32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VOP1 encoding (AMD CDNA 5).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Description

Convert from a signed 4-bit integer input to a single-precision float value using an offset table and store the result into a vector register. Used for interpolation in shader. Lookup table on S0[3:0]: S0 binary Result 1000 -0.5000f 1001 -0.4375f 1010 -0.3750f 1011 -0.3125f 1100 -0.2500f 1101 -0.1875f 1110 -0.1250f 1111 -0.0625f 0000 +0.0000f 0001 +0.0625f 0010 +0.1250f 0011 +0.1875f 0100 +0.2500f 0101 +0.3125f 0110 +0.3750f 0111 +0.4375f

Semantics

declare CVT_OFF_TABLE : 32'F[16]; D0.f32 = CVT_OFF_TABLE[S0.u32[3 : 0]]

Example

v_cvt_off_f32_i4 v5, v1

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources