v_cvt_f64_i32 GPU Native ISA AMD Vector

Vector Arithmetic

v_cvt_f64_i32

Convert from a signed 32-bit integer input to a double-precision float value and store the result into a vector register.

Encoding

Binary Layout (AMD CDNA 5)
0111111
31:25
VDST
24:17
unassigned
16
0000100
15:9
SRC0
8:0
 

The ENC_VOP1 layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 4 in OP rebuilds 0x7E000800, an identifier AMD lists for this encoding. Bits marked unassigned have no field in the specification. Not the same in every generation: AMD CDNA 4 (field layout), AMD CDNA 3 (field layout), AMD CDNA 2 (field layout), AMD CDNA 1 (field layout), AMD RDNA 3.5 (field layout), AMD RDNA 3 (field layout), AMD RDNA 2 (field layout), AMD RDNA 1 (field layout). The same in AMD RDNA 4.

Format VOP1
Width 32 bits
Opcode 4
Identifier 0x7E000800

Operands

  • VDST
    Written. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: 64-bit double-precision floating point value. (OPR_VGPR, FMT_NUM_F64)
  • SRC0
    Read. All operands. Covers all operands that are allowed as scalar or vector sources. Data format: Signed 32-bit integral data. (OPR_SRC, FMT_NUM_I32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VOP1 encoding (AMD CDNA 5).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

0ULP accuracy.

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Semantics

D0.f64 = i32_to_f64(S0.i32)

Example

v_cvt_f64_i32 v[5:6], v1

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources