v_cvt_pk_bf8_f32 GPU Native ISA AMD Vector

Vector Arithmetic

v_cvt_pk_bf8_f32

Convert from two single-precision float inputs to a packed BF8 float value with round to nearest even semantics and store the result into 16 bits of…

Encoding

Binary Layout (AMD CDNA 5)
NEG
63:61
OMOD
60:59
SRC2
58:50
SRC1
49:41
SRC0
40:32
110101
31:26
1101101010
25:16
CLAMP
15
OPSEL
14:11
ABS
10:8
VDST
7:0
 

The ENC_VOP3 layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 874 in OP rebuilds 0x00000000D76A0000, an identifier AMD lists for this encoding. Not the same in every generation: AMD CDNA 4 (opcode 675, field layout), AMD CDNA 3 (opcode 675, field layout). The same in AMD RDNA 4.

Format VOP3
Width 64 bits
Opcode 874
Identifier 0x00000000D76A0000

Operands

  • VDST
    Written. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: Packed 2-component value. (OPR_VGPR, FMT_NUM_PK2_BF8)
  • SRC0
    Read. All operands. Covers all operands that are allowed as scalar or vector sources. Data format: 32-bit single-precision floating point value. (OPR_SRC, FMT_NUM_F32)
  • SRC1
    Read. All operands. Covers all operands that are allowed as scalar or vector sources. Data format: 32-bit single-precision floating point value. (OPR_SRC, FMT_NUM_F32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VOP3 encoding (AMD CDNA 5).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Round to nearest even. Ignores OMOD and clamp.

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Description

Convert from two single-precision float inputs to a packed BF8 float value with round to nearest even semantics and store the result into 16 bits of a vector register using OPSEL.

Semantics

prev_mode = ROUND_MODE; ROUND_MODE = ROUND_NEAREST_EVEN; if OPSEL[3].u32 == 0U then VGPR[laneId][VDST.u32][15 : 0].b16 = { f32_to_bf8(S1.f32), f32_to_bf8(S0.f32) }; // D0[31:16] are preserved else VGPR[laneId][VDST.u32][31 : 16].b16 = { f32_to_bf8(S1.f32), f32_to_bf8(S0.f32) }; // D0[15:0] are preserved endif; ROUND_MODE = prev_mode

Example

v_cvt_pk_bf8_f32 v1, s2, 3

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx1170_asm_vop3-fake16.s). Not from an AMD document, and not authored here.

Sources