v_cvt_pknorm_i16_f16 GPU Native ISA AMD Vector
V CVT PKNORM I16 F16 Vector Arithmetic
v_cvt_pknorm_i16_f16
Convert from two half-precision float inputs to a packed signed normalized short and store the result into a vector register.
Encoding
Verified bit-level encoding data is not yet available for this instruction.
The instruction-format classification below (VOP3)
is well-documented and stable; exact per-target opcode/field bit positions have not
yet been imported from a verified source.
Operands
Operand details have not yet been curated for this instruction.
GFX Target Compatibility
Per-target GFX compatibility has not yet been verified for this instruction.
Related
More in Vector Arithmetic
Reference
AMDGPU / GFX ISA
Semantics
declare tmp : 32'B;
tmp[15 : 0].i16 = f16_to_snorm(S0.f16);
tmp[31 : 16].i16 = f16_to_snorm(S1.f16);
D0 = tmp.b32
Sources
- User Guide for AMDGPU Backend ↗ - LLVM Project
-
"AMD Instinct MI300" Instruction Set Architecture: Reference Guide ↗
- Advanced Micro Devices, Inc.
Reference Guide, page 367.