v_cvt_scale_pk8_bf16_fp4 GPU Native ISA AMD Vector

Vector Arithmetic

v_cvt_scale_pk8_bf16_fp4

AMDGPU VOP3 vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)

Encoding

Binary Layout (AMD CDNA 5)
NEG
63:61
OMOD
60:59
SRC2
58:50
SRC1
49:41
SRC0
40:32
110101
31:26
1010100000
25:16
CLAMP
15
OPSEL
14:11
ABS
10:8
VDST
7:0
 

The ENC_VOP3 layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 672 in OP rebuilds 0x00000000D6A00000, an identifier AMD lists for this encoding. No other generation in the specification defines this instruction.

Format VOP3
Width 64 bits
Opcode 672
Identifier 0x00000000D6A00000

Operands

  • VDST
    Written. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: 16-bit brain floating point value. Packed 8-component value. (OPR_VGPR, FMT_NUM_PK8_BF16)
  • SRC0
    Read. Operand must be a vector GPR. Uses a 9-bit operand field. Data format: Packed 8-component value. (OPR_SRC_VGPR, FMT_NUM_PK8_FP4)
  • SRC1
    Read. All operands. Covers all operands that are allowed as scalar or vector sources. Data format: Signed 8-bit integral data. Packed 4-component value. (OPR_SRC, FMT_NUM_PK4_I8)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VOP3 encoding (AMD CDNA 5).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Example

v_cvt_scale_pk8_bf16_fp4 v[10:13], v20, v8

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx1250_asm_vop3-fake16.s). Not from an AMD document, and not authored here.

Sources