v_cvt_scalef32_pk32_bf16_bf6 GPU Native ISA AMD Vector

Vector Arithmetic

v_cvt_scalef32_pk32_bf16_bf6

Convert from a packed 32-component BF6 float input to a packed BF16 float value, then scale the packed values using the exponent provided by the…

Also written as v_cvt_scale_pk_bf16_bf6. AMD's machine-readable ISA specification lists this name for the same instruction.

Encoding

Binary Layout (AMD CDNA 4)
NEG
63:61
OMOD
60:59
SRC2
58:50
SRC1
49:41
SRC0
40:32
110100
31:26
1001100011
25:16
CLAMP
15
OP_SEL
14:11
ABS
10:8
VDST
7:0
 

The ENC_VOP3 layout from AMD's machine-readable ISA specification (AMD CDNA 4). Opcode 611 in OP rebuilds 0x00000000D2630000, an identifier AMD lists for this encoding. No other generation in the specification defines this instruction.

Format VOP3
Width 64 bits
Opcode 611
Identifier 0x00000000D2630000

Operands

  • VDST
    Written. N/A Data format: N/A (OPR_VGPR, FMT_NUM_PK32_BF16)
  • SRC0
    Read. N/A Data format: N/A (OPR_SRC_VGPR, FMT_NUM_PK32_BF6)
  • SRC1
    Read. N/A Data format: N/A (OPR_SRC_SIMPLE, FMT_NUM_F32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VOP3 encoding (AMD CDNA 4).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Description

Convert from a packed 32-component BF6 float input to a packed BF16 float value, then scale the packed values using the exponent provided by the second single-precision float input. Store the result into a vector register.

Sources