v_cvt_scalef32_pk32_f32_fp6 GPU Native ISA AMD Vector
V CVT SCALEF32 PK32 F32 FP6 Vector Arithmetic
v_cvt_scalef32_pk32_f32_fp6
Convert from a packed 32-component FP6 float input to a packed single-precision float value, then scale the packed values using the exponent provided…
Encoding
Verified bit-level encoding data is not yet available for this instruction.
The instruction-format classification below (VOP3)
is well-documented and stable; exact per-target opcode/field bit positions have not
yet been imported from a verified source.
Operands
Operand details have not yet been curated for this instruction.
GFX Target Compatibility
Per-target GFX compatibility has not yet been verified for this instruction.
Related
More in Vector Arithmetic
Reference
AMDGPU / GFX ISA
Description
Convert from a packed 32-component FP6 float input to a packed single-precision float value, then scale the packed values using the exponent provided by the second single-precision float input. Store the result into a vector register.
Sources
- User Guide for AMDGPU Backend ↗ - LLVM Project
- AMD Machine-Readable GPU ISA Specification ↗ - Advanced Micro Devices, Inc.