v_cvt_scalef32_pk16_fp6_f16 GPU Native ISA AMD Vector

Vector Arithmetic

v_cvt_scalef32_pk16_fp6_f16

AMDGPU VOP3 vector instruction operating on f16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)

Encoding

Binary Layout (AMD CDNA 5)
NEG
63:61
OMOD
60:59
SRC2
58:50
SRC1
49:41
SRC0
40:32
110101
31:26
1011001111
25:16
CLAMP
15
OPSEL
14:11
ABS
10:8
VDST
7:0
 

The ENC_VOP3 layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 719 in OP rebuilds 0x00000000D6CF0000, an identifier AMD lists for this encoding. No other generation in the specification defines this instruction.

Format VOP3
Width 64 bits
Opcode 719
Identifier 0x00000000D6CF0000

Operands

  • VDST
    Written. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: Packed 16-component value. (OPR_VGPR, FMT_NUM_PK16_FP6)
  • SRC0
    Read. Operand must be a vector GPR. Uses a 9-bit operand field. Data format: 16-bit half-precision floating point value. Packed 16-component value. (OPR_SRC_VGPR, FMT_NUM_PK16_F16)
  • SRC1
    Read. All operands. Covers all operands that are allowed as scalar or vector sources. Data format: 32-bit single-precision floating point value. (OPR_SRC, FMT_NUM_F32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VOP3 encoding (AMD CDNA 5).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Example

v_cvt_scalef32_pk16_fp6_f16 v[10:12], v[20:27], v8

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx1250_asm_vop3-fake16.s). Not from an AMD document, and not authored here.

Sources