v_cvt_pk_fp8_f32 GPU Native ISA AMD Vector
V CVT PK FP8 F32 Vector Arithmetic
v_cvt_pk_fp8_f32
Convert from two single-precision float inputs to a packed FP8 float value with round to nearest even semantics and store the result into 16 bits of…
Encoding
Verified bit-level encoding data is not yet available for this instruction.
The instruction-format classification below (VOP3)
is well-documented and stable; exact per-target opcode/field bit positions have not
yet been imported from a verified source.
Operands
Operand details have not yet been curated for this instruction.
GFX Target Compatibility
| Target | Support |
|---|---|
| gfx1100 | ✅ Supported |
Round to nearest even. Ignores OMOD and clamp.
Related
More in Vector Arithmetic
Reference
AMDGPU / GFX ISA
Description
Convert from two single-precision float inputs to a packed FP8 float value with round to nearest even semantics and store the result into 16 bits of a vector register using OPSEL.
Semantics
prev_mode = ROUND_MODE;
ROUND_MODE = ROUND_NEAREST_EVEN;
if OPSEL[3].u32 == 0U then
VGPR[laneId][VDST.u32][15 : 0].b16 = { f32_to_fp8(S1.f32), f32_to_fp8(S0.f32) };
// D0[31:16] are preserved
else
VGPR[laneId][VDST.u32][31 : 16].b16 = { f32_to_fp8(S1.f32), f32_to_fp8(S0.f32) };
// D0[15:0] are preserved
endif;
ROUND_MODE = prev_mode
Sources
- User Guide for AMDGPU Backend ↗ - LLVM Project
-
"AMD Instinct MI300" Instruction Set Architecture: Reference Guide ↗
- Advanced Micro Devices, Inc.
Reference Guide, page 369.