v_cvt_pk_f32_bf8 GPU Native ISA AMD Vector

V CVT PK F32 BF8 Vector Arithmetic

v_cvt_pk_f32_bf8

Convert from a packed 2-component BF8 float input to a packed single-precision float value and store the result into a vector register.

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (VOP1) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format VOP1
Execution Unit

Operands

Operand details have not yet been curated for this instruction.

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

SDWA encoding allows SRC0_SEL to control which word of S0 is converted. Only the WORD selects of SRC0_SEL are legal. If this instruction is not encoded in SDWA then WORD0 is implied.

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Semantics

tmp = SDWA_SRC0_SEL[1 : 0] == WORD1.b2 ? S0[31 : 16] : S0[15 : 0]; D0[31 : 0].f32 = bf8_to_f32(tmp[7 : 0].bf8); D0[63 : 32].f32 = bf8_to_f32(tmp[15 : 8].bf8)

Sources