v_cvt_i16_f16 GPU Native ISA AMD Vector

V CVT I16 F16 Vector Arithmetic

v_cvt_i16_f16

Convert from a half-precision float input to a signed 16-bit integer value and store the result into a vector register.

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (VOP1) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format VOP1
Execution Unit

Operands

Operand details have not yet been curated for this instruction.

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

1ULP accuracy, supports rounding, exception flags and saturation. FP16 denormals are accepted. Conversion is done with truncation. Generation of the INEXACT exception is controlled by the CLAMP bit. INEXACT exceptions are enabled for this conversion iff CLAMP == 1.

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Semantics

D0.i16 = f16_to_i16(S0.f16)

Example

v_cvt_i16_f16 v5.l, s1

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.

Sources