v_cvt_f32_bf8 GPU Native ISA AMD Vector

V CVT F32 BF8 Vector Arithmetic

v_cvt_f32_bf8

Convert from a BF8 float input to a single-precision float value and store the result into a vector register.

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (VOP1) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format VOP1
Execution Unit

Operands

Operand details have not yet been curated for this instruction.

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

SDWA encoding allows SRC0_SEL to control which byte of S0 is converted. Only the BYTE selects of SRC0_SEL are legal. If this instruction is not encoded in SDWA then BYTE0 is implied.

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Semantics

if SDWA_SRC0_SEL == BYTE1.b3 then D0.f32 = bf8_to_f32(S0[15 : 8].bf8) elsif SDWA_SRC0_SEL == BYTE2.b3 then D0.f32 = bf8_to_f32(S0[23 : 16].bf8) elsif SDWA_SRC0_SEL == BYTE3.b3 then D0.f32 = bf8_to_f32(S0[31 : 24].bf8) else // BYTE0 implied D0.f32 = bf8_to_f32(S0[7 : 0].bf8) endif

Sources