v_clrexcp GPU Native ISA AMD Vector

Vector Arithmetic

v_clrexcp

Clear this wave's exception state in the vector ALU.

Encoding

Binary Layout (AMD CDNA 4)

0111111

31:25

VDST

24:17

00110101

16:9

SRC0

8:0

The ENC_VOP1 layout from AMD's machine-readable ISA specification (AMD CDNA 4). Opcode 53 in OP rebuilds 0x7E006A00, an identifier AMD lists for this encoding. Not the same in every generation: AMD RDNA 2 (opcode 65), AMD RDNA 1 (opcode 65). The same in AMD CDNA 3, AMD CDNA 2, AMD CDNA 1.

Format VOP1

Width 32 bits

Opcode 53

Identifier 0x7E006A00

Operands

Operand details have not yet been curated for this instruction.

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Reference

AMDGPU / GFX ISA

Sources

User Guide for AMDGPU Backend ↗ - LLVM Project
"AMD Instinct MI300" Instruction Set Architecture: Reference Guide ↗ - Advanced Micro Devices, Inc.
Reference Guide, page 203.
AMD Machine-Readable GPU ISA Specification ↗ - Advanced Micro Devices, Inc.