v_bfi_b32 GPU Native ISA AMD Vector

V BFI B32 Vector Arithmetic

v_bfi_b32

Overwrite a bitfield in the third input with a bitfield from the second input using a mask from the first input, then store the result into a vector…

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (VOP3) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format VOP3
Execution Unit

Operands

Operand details have not yet been curated for this instruction.

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related PTX Concepts

Bit-Field Insert ↗
equivalent with restrictions
bfi (PTX)

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Description

Overwrite a bitfield in the third input with a bitfield from the second input using a mask from the first input, then store the result into a vector register.

Semantics

D0.u32 = ((S0.u32 & S1.u32) | (~S0.u32 & S2.u32))

Example

v_bfi_b32 v5, v1, v2, s3

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.

Sources