v_cvt_pknorm_i16_f32 GPU Native ISA AMD Vector

Vector Arithmetic

v_cvt_pknorm_i16_f32

Convert from two single-precision float inputs to a packed signed normalized short and store the result into a vector register.

Also written as v_cvt_pk_norm_i16_f32. AMD's machine-readable ISA specification lists this name for the same instruction.

Encoding

Binary Layout (AMD CDNA 4)
NEG
63:61
OMOD
60:59
SRC2
58:50
SRC1
49:41
SRC0
40:32
110100
31:26
1010010100
25:16
CLAMP
15
OP_SEL
14:11
ABS
10:8
VDST
7:0
 

The ENC_VOP3 layout from AMD's machine-readable ISA specification (AMD CDNA 4). Opcode 660 in OP rebuilds 0x00000000D2940000, an identifier AMD lists for this encoding. Not the same in every generation: AMD RDNA 2 (layout not verifiable), AMD RDNA 1 (layout not verifiable). The same in AMD CDNA 3, AMD CDNA 2, AMD CDNA 1.

Format VOP2
Width 64 bits
Opcode 660
Identifier 0x00000000D2940000

Operands

  • VDST
    Written. N/A Data format: N/A (OPR_VGPR, FMT_NUM_PK2_I16)
  • SRC0
    Read. N/A Data format: N/A (OPR_SRC_NOLIT, FMT_NUM_F32)
  • SRC1
    Read. N/A Data format: N/A (OPR_SRC_SIMPLE, FMT_NUM_F32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VOP3 encoding (AMD CDNA 4).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Example

v_cvt_pknorm_i16_f32 v5, 0, v2

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx7_asm_vop2.s). Not from an AMD document, and not authored here.

Sources