v_add_i32 GPU Native ISA AMD Vector

Vector Arithmetic

v_add_i32

Add two signed 32-bit integer inputs and store the result into a vector register. No carry-in or carry-out support.

Encoding

Binary Layout (AMD CDNA 4)
NEG
63:61
OMOD
60:59
SRC2
58:50
SRC1
49:41
SRC0
40:32
110100
31:26
1010011100
25:16
CLAMP
15
OP_SEL
14:11
ABS
10:8
VDST
7:0
 

The ENC_VOP3 layout from AMD's machine-readable ISA specification (AMD CDNA 4). Opcode 668 in OP rebuilds 0x00000000D29C0000, an identifier AMD lists for this encoding. The same in the other 3 generations that define it.

Format VOP2
Width 64 bits
Opcode 668
Identifier 0x00000000D29C0000

Operands

  • VDST
    Written. N/A Data format: N/A (OPR_VGPR, FMT_NUM_I32)
  • SRC0
    Read. N/A Data format: N/A (OPR_SRC_NOLIT, FMT_NUM_I32)
  • SRC1
    Read. N/A Data format: N/A (OPR_SRC_SIMPLE, FMT_NUM_I32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VOP3 encoding (AMD CDNA 4).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Example

v_add_i32 v5, 0, v2

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx9_asm_vop3_e64.s). Not from an AMD document, and not authored here.

Sources