Warp-Level Reduction Warp/Wavefront-Level

Combine one value per lane into a single result for the whole warp or wavefront.

Vendor-Neutral Definition

A tree or butterfly reduction across lanes under an associative operator, without going through shared memory.
⚠️ Cross-vendor mappings describe semantic relationships and are not guaranteed one-to-one compiler translations.
equivalent sequence PTX has a single-instruction reduction on newer targets. AMDGPU builds the same result from a logarithmic sequence of cross-lane moves and arithmetic.
Property NVIDIA PTX AMDGPU
Instruction redux.sync ds_swizzle_b32, v_add_f32
ISA Layer Virtual Native
Data Types - b32, f32
Version / Target Introduced PTX ISA 7.0 gfx1100, gfx942/gfx1100

Important Differences

  • redux.sync reduces in one instruction but is limited to integer operations and requires sm_80 or later; older targets use the same shuffle-and-combine loop AMDGPU uses.
  • The AMDGPU idiom is log2(wavefront size) steps of a cross-lane permute followed by the operator, using ds_swizzle_b32 or DPP row and bank modifiers on the arithmetic instruction itself. DPP folds the data movement into the ALU instruction, which has no PTX equivalent.
  • Because it is a sequence rather than one instruction, the exact form is a compiler and library decision, so a mapping here identifies the building blocks rather than a fixed translation.

Source Evidence

Verification method: documentation