redux.sync GPU Virtual ISA NVIDIA

redux.sync Parallel Synchronization and Communication Instructions

redux.sync.op.type dst, src, membermask;

redux.sync will cause the executing thread to wait until all non-exited threads corresponding to membermask have executed redux.sync with the same qualifiers and same membermask value before resuming execution.

Encoding

PTX is a virtual instruction set. It has no single, stable native binary encoding - the compiler lowers this instruction to different native machine code depending on the selected NVIDIA target architecture (compute capability). This page intentionally shows no bit-diagram; see the target/version requirements below for what governs how this instruction compiles.
PTX ISA Version Introduced PTX ISA 7.0
Minimum Target sm_80

Syntax Forms

One mnemonic covers many type / state-space / scope / modifier combinations - each row below is an independently valid form.

Syntax Data Types State Space(s) Modifiers Min. Target Description
redux.sync.op.type dst, src, membermask; sm_80 redux.sync will cause the executing thread to wait until all non-exited threads corresponding to membermask have executed redux. (see the official PTX ISA docs for the full description)

Operands

  • dst
    Operand
  • src
    Operand
  • membermask
    Operand

At a Glance

Data Types -

Related

More in Parallel Synchronization and Communication Instructions

Reference

NVIDIA PTX ISA

Description

redux.sync will cause the executing thread to wait until all non-exited threads corresponding to membermask have executed redux.sync with the same qualifiers and same membermask value before resuming execution. Operand membermask specifies a 32-bit integer which is a mask indicating threads participating in this instruction where the bit position corresponds to thread’s laneid. redux.sync performs a reduction operation.op of the 32 bit source register src across all non-exited threads in the membermask. (see the official PTX ISA docs for the full description)

Examples

.reg .b32 dst, src, init, mask;
redux.sync.add.s32 dst, src, 0xff;
redux.sync.xor.b32 dst, src, mask;

redux.sync.min.abs.NaN.f32 dst, src, mask;

Reproduced from NVIDIA's official PTX ISA documentation for technical accuracy.

Sources