mbarrier.arrive_drop GPU Virtual ISA NVIDIA

mbarrier.arrive_drop Parallel Synchronization and Communication Instructions

mbarrier.arrive_drop{.sem.scope}{.shared{::cta}}.b64 state, [addr] {, count};

A thread executing mbarrier.arrive_drop on the mbarrier object at the location specified by the address operand addr performs the following steps: Decrements the expected arrival count of the mbarrier object by the value specified by the 32-bit integer operand count.

Encoding

PTX is a virtual instruction set. It has no single, stable native binary encoding - the compiler lowers this instruction to different native machine code depending on the selected NVIDIA target architecture (compute capability). This page intentionally shows no bit-diagram; see the target/version requirements below for what governs how this instruction compiles.
PTX ISA Version Introduced PTX ISA 7.0
Minimum Target sm_80

Syntax Forms

One mnemonic covers many type / state-space / scope / modifier combinations - each row below is an independently valid form.

Syntax Data Types State Space(s) Modifiers Min. Target Description
mbarrier.arrive_drop{.sem.scope}{.shared{::cta}}.b64 state, [addr] {, count}; sm_80 A thread executing mbarrier.arrive_drop on the mbarrier object at the location specified by the address operand addr performs the following steps: Decrements the expected arrival count of the mbarrier… (see the official PTX ISA docs for the full description)

Operands

At a Glance

Data Types -

Related

More in Parallel Synchronization and Communication Instructions

Reference

NVIDIA PTX ISA

Description

A thread executing mbarrier.arrive_drop on the mbarrier object at the location specified by the address operand addr performs the following steps: Decrements the expected arrival count of the mbarrier object by the value specified by the 32-bit integer operand count. If count operand is not specified, it defaults to 1. Performs an arrive-on operation on the mbarrier object. The operand count specifies the count argument to the arrive-on operation. The decrement done in the expected arrivals count of the mbarrier object will be for all the subsequent phases of the mbarrier object. If no state space is specified then Generic Addressing is used. (see the official PTX ISA docs for the full description)

Examples

.reg .b32 cnt;
.reg .b64 %r1;
.shared .b64 shMem;

// Example 1
@p mbarrier.arrive_drop.shared.b64 _, [shMem];
// (truncated - see the official PTX ISA docs for the full example)

Reproduced from NVIDIA's official PTX ISA documentation for technical accuracy.

Sources