mbarrier.pending_count GPU Virtual ISA NVIDIA

mbarrier.pending_count Parallel Synchronization and Communication Instructions

mbarrier.pending_count{.layout}.b64 count, state;

The pending count can be queried from the opaque mbarrier state using mbarrier.pending_count.

Encoding

PTX is a virtual instruction set. It has no single, stable native binary encoding - the compiler lowers this instruction to different native machine code depending on the selected NVIDIA target architecture (compute capability). This page intentionally shows no bit-diagram; see the target/version requirements below for what governs how this instruction compiles.
PTX ISA Version Introduced PTX ISA 7.0
Minimum Target sm_80

Syntax Forms

One mnemonic covers many type / state-space / scope / modifier combinations - each row below is an independently valid form.

Syntax Data Types State Space(s) Modifiers Min. Target Description
mbarrier.pending_count{.layout}.b64 count, state; sm_80 The pending count can be queried from the opaque mbarrier state using mbarrier.pending_count. The state operand is a 64-bit register that must be the result of a prior mbarrier.arrive. (see the official PTX ISA docs for the full description)

Operands

  • count
    Operand
  • state
    Operand

At a Glance

Data Types -

Related

More in Parallel Synchronization and Communication Instructions

Reference

NVIDIA PTX ISA

Description

The pending count can be queried from the opaque mbarrier state using mbarrier.pending_count. The state operand is a 64-bit register that must be the result of a prior mbarrier.arrive.noComplete or mbarrier.arrive_drop.noComplete instruction. Otherwise, the behavior is undefined. The destination register count is a 32-bit unsigned integer representing the pending count of the mbarrier object prior to the arrive-on operation from which the state register was obtained. The optional qualifier.layout::v0 denotes the layout of the corresponding mbarrier object as described in the section Layouts of the mbarrier object.

Examples

.reg .b32 %r1;
.reg .b64 state;
.shared .b64 shMem;

mbarrier.arrive.noComplete.b64 state, [shMem], 1;
mbarrier.pending_count.layout::v0.b64 %r1, state;

Reproduced from NVIDIA's official PTX ISA documentation for technical accuracy.

Sources