min GPU Virtual ISA NVIDIA

Minimum Arithmetic

min.type d, a, b;

Select the smaller of two operands.

Encoding

PTX is a virtual instruction set. It has no single, stable native binary encoding - the compiler lowers this instruction to different native machine code depending on the selected NVIDIA target architecture (compute capability). This page intentionally shows no bit-diagram; see the target/version requirements below for what governs how this instruction compiles.
PTX ISA Version Introduced PTX ISA 1.0
Minimum Target sm_10

Syntax Forms

One mnemonic covers many type / state-space / scope / modifier combinations - each row below is an independently valid form.

Syntax Data Types State Space(s) Modifiers Min. Target Description
min.type d, a, b; s16, s32, s64, u16, u32, u64, f32, f64 sm_10 Integer or floating-point minimum.

Operands

  • d
    Destination register
  • a
    First operand
  • b
    Second operand

At a Glance

Data Types f32, f64, s16, s32, s64, u16, u32, u64

Related AMDGPU Concepts

Minimum ↗
equivalent with restrictions
v_min_f32 (AMDGPU)
v_min_i32 (AMDGPU)
v_min_u32 (AMDGPU)

Related

More in Arithmetic

Reference

NVIDIA PTX ISA

Description

Store the minimum of a and b in d. For.f16x2 and.bf16x2 instruction types, input vectors are formed with half-word values from source operands. Half-word operands are then processed in parallel to store.f16x2 or.bf16x2 result in destination. For.f16 instruction type, operands d and a have.f16 or.b16 type. For.f16x2 instruction type, operands d and a have.f16x2 or.b32 type. For.bf16 instruction type, operands d and a have.b16 type. (see the official PTX ISA docs for the full description)

Semantics

d = (a < b) ? a : b, with type-specific NaN-handling rules for floating-point forms.

Examples

min.s32  r0,a,b;
@p  min.u16  h,i,j;
    min.s16x2.relu u,v,w;
    min.u8x4 p, q, r;

@p  min.ftz.f32  z,z,x;
    min.f64      a,b,c;
    // fp32 min with .NaN
    min.NaN.f32  f0,f1,f2;
    // fp32 min with .xorsign.abs
    min.xorsign.abs.f32 Rd, Ra, Rb;

min.ftz.f16       h0,h1,h2;
min.f16x2         b0,b1,b2;
// SIMD fp16 min with .NaN
min.NaN.f16x2     b0,b1,b2;
min.bf16          h0, h1, h2;
// SIMD bf16 min with NaN
// (truncated - see the official PTX ISA docs for the full example)

Reproduced from NVIDIA's official PTX ISA documentation for technical accuracy.

Sources