mad GPU Virtual ISA NVIDIA

Multiply-Add Arithmetic

mad.mode.stype d, a, b, c;

Compute (a * b) + c as two rounding steps (unlike fma, which fuses them into one).

Encoding

PTX is a virtual instruction set. It has no single, stable native binary encoding - the compiler lowers this instruction to different native machine code depending on the selected NVIDIA target architecture (compute capability). This page intentionally shows no bit-diagram; see the target/version requirements below for what governs how this instruction compiles.
PTX ISA Version Introduced PTX ISA 1.0
Minimum Target sm_10

Syntax Forms

One mnemonic covers many type / state-space / scope / modifier combinations - each row below is an independently valid form.

Syntax Data Types State Space(s) Modifiers Min. Target Description
mad.mode.stype d, a, b, c; s16, s32, s64, u16, u32, u64 lo, hi, wide sm_10 Integer multiply-add.
mad.f32 d, a, b, c; f32 sm_10 Single-precision floating-point multiply-add (not fused).

Operands

  • d
    Destination register
  • a
    Multiplicand
  • b
    Multiplier
  • c
    Addend

At a Glance

Data Types f32, s16, s32, s64, u16, u32, u64
Modifiers hi, lo, wide

Related AMDGPU Concepts

Multiply-Add (Unfused) ↗
equivalent with restrictions
v_mad_f32 (AMDGPU)

Related

More in Arithmetic

Reference

NVIDIA PTX ISA

Description

Multiplies two values, optionally extracts the high or low half of the intermediate result, and adds a third value. Writes the result into a destination register.

Semantics

d = (a * b) + c.

Examples

@p  mad.lo.s32 d,a,b,c;
    mad.lo.s32 r,p,q,r;

@p  mad.f32  d,a,b,c;

Reproduced from NVIDIA's official PTX ISA documentation for technical accuracy.

Sources