v_mad_f32 GPU Native ISA AMD Vector

V MAD F32 Vector Arithmetic

v_mad_f32

Multiply two single-precision float inputs and add a third input, and store the result into a vector register.

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (VOP3) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.

Format VOP3

Execution Unit

Operands

Operand details have not yet been curated for this instruction.

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related PTX Concepts

Multiply-Add (Unfused) ↗

equivalent with restrictions

mad (PTX)

Reference

AMDGPU / GFX ISA

Sources

User Guide for AMDGPU Backend ↗ - LLVM Project
AMD Machine-Readable GPU ISA Specification ↗ - Advanced Micro Devices, Inc.