v_madak_f16 GPU Native ISA AMD Vector
V MADAK F16 Vector Arithmetic
v_madak_f16
Multiply two floating point inputs and add a literal constant, and store the result into a vector register. Implements IEEE rules.
Encoding
Verified bit-level encoding data is not yet available for this instruction.
The instruction-format classification below (VOP2)
is well-documented and stable; exact per-target opcode/field bit positions have not
yet been imported from a verified source.
Operands
Operand details have not yet been curated for this instruction.
GFX Target Compatibility
Per-target GFX compatibility has not yet been verified for this instruction.
This opcode cannot use the VOP3 encoding and cannot use input/output modifiers. Supports round mode, exception flags, saturation.
Related
More in Vector Arithmetic
Reference
AMDGPU / GFX ISA
Semantics
tmp = S0.f16 * S1.f16 + SIMM16.f16;
D0 = { 16'0, tmp.f16 }
Sources
- User Guide for AMDGPU Backend ↗ - LLVM Project
-
"AMD Instinct MI300" Instruction Set Architecture: Reference Guide ↗
- Advanced Micro Devices, Inc.
Reference Guide, page 179.