v_mad_i64_i32 GPU Native ISA AMD Vector

Vector Arithmetic

v_mad_i64_i32

Multiply two signed integer inputs, add a third signed integer input, store the result into a 64-bit vector register and store the overflow/carryout…

Also written as v_mad_co_i64_i32. AMD's machine-readable ISA specification lists this name for the same instruction.

Encoding

Binary Layout (AMD CDNA 4)
NEG
63:61
OMOD
60:59
SRC2
58:50
SRC1
49:41
SRC0
40:32
110100
31:26
0111101001
25:16
CLAMP
15
SDST
14:8
VDST
7:0
 

The VOP3_SDST_ENC layout from AMD's machine-readable ISA specification (AMD CDNA 4). Opcode 489 in OP rebuilds 0x00000000D1E90000, an identifier AMD lists for this encoding. Not the same in every generation: AMD RDNA 3.5 (layout not verifiable), AMD RDNA 3 (layout not verifiable), AMD RDNA 2 (layout not verifiable), AMD RDNA 1 (layout not verifiable). The same in AMD CDNA 3, AMD CDNA 2, AMD CDNA 1.

Format VOP3
Width 64 bits
Opcode 489
Identifier 0x00000000D1E90000

Operands

  • VDST
    Written. N/A Data format: N/A (OPR_VGPR, FMT_NUM_I64)
  • SDST
    Written. N/A Data format: N/A (OPR_SREG, FMT_NUM_M64)
  • SRC0
    Read. N/A Data format: N/A (OPR_SRC_NOLIT, FMT_NUM_I32)
  • SRC1
    Read. N/A Data format: N/A (OPR_SRC_SIMPLE, FMT_NUM_I32)
  • SRC2
    Read. N/A Data format: N/A (OPR_SRC_SIMPLE, FMT_NUM_I64)

In AMD's order, as its machine-readable ISA specification lists them for the VOP3_SDST_ENC encoding (AMD CDNA 4).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

In VOP3 the VCC destination may be an arbitrary SGPR-pair.

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Description

Multiply two signed integer inputs, add a third signed integer input, store the result into a 64-bit vector register and store the overflow/carryout into a scalar mask register.

Semantics

{ D1.i1, D0.i64 } = 65'B(65'I(S0.i32) * 65'I(S1.i32) + 65'I(S2.i64))

Example

v_mad_i64_i32 v[5:6], s6, s105, s105, s[6:7]

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources