v_mad_f16 GPU Native ISA AMD Vector

Vector Arithmetic

v_mad_f16

Multiply two half-precision float inputs and add a third input, and store the result into a vector register.

Encoding

Binary Layout (AMD CDNA 4)
NEG
63:61
OMOD
60:59
SRC2
58:50
SRC1
49:41
SRC0
40:32
110100
31:26
1000000011
25:16
CLAMP
15
OP_SEL
14:11
ABS
10:8
VDST
7:0
 

The ENC_VOP3 layout from AMD's machine-readable ISA specification (AMD CDNA 4). Opcode 515 in OP rebuilds 0x00000000D2030000, an identifier AMD lists for this encoding. The same in the other 3 generations that define it.

Format VOP3
Width 64 bits
Opcode 515
Identifier 0x00000000D2030000

Operands

  • VDST
    Written. N/A Data format: N/A (OPR_VGPR, FMT_NUM_F16)
  • SRC0
    Read. N/A Data format: N/A (OPR_SRC_NOLIT, FMT_NUM_F16)
  • SRC1
    Read. N/A Data format: N/A (OPR_SRC_SIMPLE, FMT_NUM_F16)
  • SRC2
    Read. N/A Data format: N/A (OPR_SRC_SIMPLE, FMT_NUM_F16)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VOP3 encoding (AMD CDNA 4).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Supports round mode, exception flags, saturation. 1ULP accuracy, denormals are flushed. If OPSEL[3] is 0 Result is written to 16 LSBs of destination VGPR and hi 16 bits are preserved. If OPSEL[3] is 1 Result is written to 16 MSBs of destination VGPR and lo 16 bits are preserved.

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Semantics

D0.f16 = S0.f16 * S1.f16 + S2.f16

Example

v_mad_f16 v5, 0, v2, v3

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx8_asm_vop3_e64.s). Not from an AMD document, and not authored here.

Sources