v_lerp_u8 GPU Native ISA AMD Vector

Vector Arithmetic

v_lerp_u8

Average two 4-D vectors stored as packed bytes in the first two inputs with rounding control provided by the third input, then store the result into…

Encoding

Binary Layout (AMD CDNA 5)
NEG
63:61
OMOD
60:59
SRC2
58:50
SRC1
49:41
SRC0
40:32
110101
31:26
1000010101
25:16
CLAMP
15
OPSEL
14:11
ABS
10:8
VDST
7:0
 

The ENC_VOP3 layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 533 in OP rebuilds 0x00000000D6150000, an identifier AMD lists for this encoding. Not the same in every generation: AMD CDNA 4 (opcode 461, field layout), AMD CDNA 3 (opcode 461, field layout), AMD CDNA 2 (opcode 461, field layout), AMD CDNA 1 (opcode 461, field layout), AMD RDNA 3.5 (field layout), AMD RDNA 3 (field layout), AMD RDNA 2 (opcode 333, field layout), AMD RDNA 1 (opcode 333, field layout). The same in AMD RDNA 4.

Format VOP3
Width 64 bits
Opcode 533
Identifier 0x00000000D6150000

Operands

  • VDST
    Written. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: Unsigned 32-bit integral data. (OPR_VGPR, FMT_NUM_U32)
  • SRC0
    Read. All operands. Covers all operands that are allowed as scalar or vector sources. Data format: 32 bits of arbitrary data. (OPR_SRC, FMT_NUM_B32)
  • SRC1
    Read. All operands. Covers all operands that are allowed as scalar or vector sources. Data format: 32 bits of arbitrary data. (OPR_SRC, FMT_NUM_B32)
  • SRC2
    Read. All operands. Covers all operands that are allowed as scalar or vector sources. Data format: 32 bits of arbitrary data. (OPR_SRC, FMT_NUM_B32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VOP3 encoding (AMD CDNA 5).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Description

Average two 4-D vectors stored as packed bytes in the first two inputs with rounding control provided by the third input, then store the result into a vector register. Each byte in the third input acts as a rounding mode for the corresponding element; if the LSB is set then 0.5 rounds up, otherwise 0.5 truncates.

Semantics

tmp = ((S0.u32[31 : 24] + S1.u32[31 : 24] + S2.u32[24].u8) >> 1U << 24U); tmp += ((S0.u32[23 : 16] + S1.u32[23 : 16] + S2.u32[16].u8) >> 1U << 16U); tmp += ((S0.u32[15 : 8] + S1.u32[15 : 8] + S2.u32[8].u8) >> 1U << 8U); tmp += ((S0.u32[7 : 0] + S1.u32[7 : 0] + S2.u32[0].u8) >> 1U); D0.u32 = tmp.u32

Example

v_lerp_u8 v5, v1, v2, s3

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources