v_fmamk_f32 GPU Native ISA AMD Vector
V FMAMK F32 Vector Arithmetic
v_fmamk_f32
Multiply a single-precision float input with a literal constant and add a second single-precision float input using fused multiply add, and store the…
Encoding
Verified bit-level encoding data is not yet available for this instruction.
The instruction-format classification below (VOP2)
is well-documented and stable; exact per-target opcode/field bit positions have not
yet been imported from a verified source.
Operands
Operand details have not yet been curated for this instruction.
GFX Target Compatibility
| Target | Support |
|---|---|
| gfx1100 | ✅ Supported |
| gfx942 | ✅ Supported |
This opcode cannot use the VOP3 encoding and cannot use input/output modifiers.
Related
More in Vector Arithmetic
Reference
AMDGPU / GFX ISA
Description
Multiply a single-precision float input with a literal constant and add a second single-precision float input using fused multiply add, and store the result into a vector register.
Semantics
D0.f32 = fma(S0.f32, SIMM32.f32, S1.f32)
Example
v_fmamk_f32 v5, -1, 0xaf123456, v3A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.
Sources
- User Guide for AMDGPU Backend ↗ - LLVM Project
-
"AMD Instinct MI300" Instruction Set Architecture: Reference Guide ↗
- Advanced Micro Devices, Inc.
Reference Guide, page 174. - LLVM MC assembler tests for AMDGPU (gfx11) ↗ - LLVM Project