v_fmamk_f32 GPU Native ISA AMD Vector

Vector Arithmetic

v_fmamk_f32

Multiply a single-precision float input with a literal constant and add a second single-precision float input using fused multiply add, and store the…

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (VOP2) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format VOP2

Operands

  • 1: VGPR
    Vector general-purpose register, one value per lane. Written v5 in the assembler example.
  • 2: immediate
    Literal value encoded in the instruction. Written -1 in the assembler example.
  • 3: immediate
    Literal value encoded in the instruction. Written 0xaf123456 in the assembler example.
  • 4: VGPR
    Vector general-purpose register, one value per lane. Written v3 in the assembler example.

Register classes read from the LLVM assembler example on this page. No source this site uses names these operands, so no names are given.

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported
gfx942✅ Supported

This opcode cannot use the VOP3 encoding and cannot use input/output modifiers.

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Description

Multiply a single-precision float input with a literal constant and add a second single-precision float input using fused multiply add, and store the result into a vector register.

Semantics

D0.f32 = fma(S0.f32, SIMM32.f32, S1.f32)

Example

v_fmamk_f32 v5, -1, 0xaf123456, v3

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources