v_fmac_f64 GPU Native ISA AMD Vector

Vector Arithmetic

v_fmac_f64

Multiply two floating point inputs and accumulate the result into the destination register using fused multiply add.

Encoding

Binary Layout (AMD CDNA 5)
0
31
010111
30:25
VDST
24:17
VSRC1
16:9
SRC0
8:0
 

The ENC_VOP2 layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 23 in OP rebuilds 0x2E000000, an identifier AMD lists for this encoding. Not the same in every generation: AMD CDNA 4 (opcode 4), AMD CDNA 3 (opcode 4), AMD CDNA 2 (opcode 4).

Format VOP2
Width 32 bits
Opcode 23
Identifier 0x2E000000

Operands

  • VDST
    Written. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: 64-bit double-precision floating point value. (OPR_VGPR, FMT_NUM_F64)
  • SRC0
    Read. All operands. Covers all operands that are allowed as scalar or vector sources. Data format: 64-bit double-precision floating point value. (OPR_SRC, FMT_NUM_F64)
  • VSRC1
    Read. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: 64-bit double-precision floating point value. (OPR_VGPR, FMT_NUM_F64)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VOP2 encoding (AMD CDNA 5).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Semantics

D0.f64 = fma(S0.f64, S1.f64, D0.f64)

Sources