v_fmac_f64 GPU Native ISA AMD Vector
V FMAC F64 Vector Arithmetic
v_fmac_f64
Multiply two floating point inputs and accumulate the result into the destination register using fused multiply add.
Encoding
Verified bit-level encoding data is not yet available for this instruction.
The instruction-format classification below (VOP2)
is well-documented and stable; exact per-target opcode/field bit positions have not
yet been imported from a verified source.
Operands
Operand details have not yet been curated for this instruction.
GFX Target Compatibility
Per-target GFX compatibility has not yet been verified for this instruction.
Related
More in Vector Arithmetic
Reference
AMDGPU / GFX ISA
Semantics
D0.f64 = fma(S0.f64, S1.f64, D0.f64)
Sources
- User Guide for AMDGPU Backend ↗ - LLVM Project
-
"AMD Instinct MI300" Instruction Set Architecture: Reference Guide ↗
- Advanced Micro Devices, Inc.
Reference Guide, page 170.