v_exp_f16 GPU Native ISA AMD Vector
V EXP F16 Vector Arithmetic
v_exp_f16
Calculate 2 raised to the power of the half-precision float input and store the result into a vector register.
Encoding
Verified bit-level encoding data is not yet available for this instruction.
The instruction-format classification below (VOP1)
is well-documented and stable; exact per-target opcode/field bit positions have not
yet been imported from a verified source.
Operands
Operand details have not yet been curated for this instruction.
GFX Target Compatibility
Per-target GFX compatibility has not yet been verified for this instruction.
1ULP accuracy, denormals are supported.
Related
More in Vector Arithmetic
Reference
AMDGPU / GFX ISA
Semantics
D0.f16 = pow(16'2.0, S0.f16)
Example
V_EXP_F16(0xfc00) => 0x0000 // exp(-INF) = 0
V_EXP_F16(0x8000) => 0x3c00 // exp(-0.0) = 1
V_EXP_F16(0x7c00) => 0x7c00 // exp(+INF) = +INFReproduced from AMD's official "AMD Instinct MI300" ISA Reference Guide for technical accuracy.
Sources
- User Guide for AMDGPU Backend ↗ - LLVM Project
-
"AMD Instinct MI300" Instruction Set Architecture: Reference Guide ↗
- Advanced Micro Devices, Inc.
Reference Guide, page 207.