v_dual_mov_b32 GPU Native ISA AMD Vector

Vector Arithmetic

v_dual_mov_b32

Move 32-bit data from a vector input into a vector register.

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (VOPD) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format VOPD

Operands

Operand details have not yet been curated for this instruction.

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Example

v_dual_mov_b32 v255, v4 :: v_dual_max_num_f32 v6, v1, v255

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx1170_asm_vopd.s). Not from an AMD document, and not authored here.

Sources